A New Five-Phase Inverter Topology With Reduced Common-Mode Voltage

Several research on the two-level (2L) fivephase inverter have been conducted to minimize the peakto- peak value of the common-mode voltage (CMV), resulting in a 20%-80% reduction in it. Nonetheless, the step change in CMV (ΔCMV) is V dc/5, which is the same as in the standard space vector pulse width modulation (SVPWM). To reduce ΔCMV and obtain a better harmonic performance, multilevel inverters (MLIs) were proposed in the literature. However, there is a noticeable increase in complexity when dealing with multiphase systems and MLIs. Hence, this article proposes a new five-phase inverter to minimize ΔCMV, the peak-to-peak value and the number of transitions of CMV, and the number of semiconductor switches. The proposed structure consists of one 3-level leg and four 2-level legs, achieving an optimal balance between complexity and performance. To control the new inverter, a new SVPWM approach is developed to achieve the following goals: 1) reduce ΔCMV to Vdc/10 instead of Vdc/5 in the case of 2L inverters; 2) minimize the CMV peak-to-peak value by 80% relative to standard topologies; and 3) minimize the number of CMV transitions per switching cycle. Additionally, the inverter achieves self-balancing of the neutral-point voltage (NPV). Furthermore, the proposed inverter is compared with existing solutions using both experimental and MATLAB simulations.