A multiple valued logic approach for the synthesis of garbled circuits

Stelvio Cimato; Valentina Ciriani; Ernesto Damiani; Maryam Ehsanpour

doi:10.1109/VLSI-SoC.2017.8203495

A multiple valued logic approach for the synthesis of garbled circuits

Stelvio Cimato, Valentina Ciriani, Ernesto Damiani, Maryam Ehsanpour

Electrical Engineering

Università degli Studi di Milano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Secure Multi-party Computation (SMC) protocols enable two or more parties to compute collaboratively generic functions while keeping secret their inputs, sharing only the final result. To achieve this goal, a technique relying on the design of Garbled Circuits (GC) has been firstly proposed by Yao. Garbled circuits are Boolean circuits that can be evaluated using a distributed protocol for computing the result for each gate, till computing the output values. To improve the efficiency of this technique and exploit SMC protocols in practical applications, such as computation outsourcing in untrusted environments, a number of optimizations have been introduced. In this paper we analyze the deployment of Multiple Valued Logic techniques for the design of GC, discussing their impact on the overall computation and communication costs.

Original language	British English
Title of host publication	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538628805
DOIs	https://doi.org/10.1109/VLSI-SoC.2017.8203495
State	Published - 13 Dec 2017
Event	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates Duration: 23 Oct 2017 → 25 Oct 2017

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	23/10/17 → 25/10/17

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10.1109/VLSI-SoC.2017.8203495

Cite this

Cimato, S., Ciriani, V., Damiani, E., & Ehsanpour, M. (2017). A multiple valued logic approach for the synthesis of garbled circuits. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings Article 8203495 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203495

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title = "A multiple valued logic approach for the synthesis of garbled circuits",

abstract = "Secure Multi-party Computation (SMC) protocols enable two or more parties to compute collaboratively generic functions while keeping secret their inputs, sharing only the final result. To achieve this goal, a technique relying on the design of Garbled Circuits (GC) has been firstly proposed by Yao. Garbled circuits are Boolean circuits that can be evaluated using a distributed protocol for computing the result for each gate, till computing the output values. To improve the efficiency of this technique and exploit SMC protocols in practical applications, such as computation outsourcing in untrusted environments, a number of optimizations have been introduced. In this paper we analyze the deployment of Multiple Valued Logic techniques for the design of GC, discussing their impact on the overall computation and communication costs.",

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Cimato, S, Ciriani, V, Damiani, E & Ehsanpour, M 2017, A multiple valued logic approach for the synthesis of garbled circuits. in 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings., 8203495, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, 23/10/17. https://doi.org/10.1109/VLSI-SoC.2017.8203495

A multiple valued logic approach for the synthesis of garbled circuits. / Cimato, Stelvio; Ciriani, Valentina; Damiani, Ernesto et al.
25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. 8203495 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Secure Multi-party Computation (SMC) protocols enable two or more parties to compute collaboratively generic functions while keeping secret their inputs, sharing only the final result. To achieve this goal, a technique relying on the design of Garbled Circuits (GC) has been firstly proposed by Yao. Garbled circuits are Boolean circuits that can be evaluated using a distributed protocol for computing the result for each gate, till computing the output values. To improve the efficiency of this technique and exploit SMC protocols in practical applications, such as computation outsourcing in untrusted environments, a number of optimizations have been introduced. In this paper we analyze the deployment of Multiple Valued Logic techniques for the design of GC, discussing their impact on the overall computation and communication costs.

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A multiple valued logic approach for the synthesis of garbled circuits

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