A maximally stable extremal regions system-on-chip for real-time visual surveillance

Ehab Salahat; Hani Saleh; Andrzej Sluzek; Mahmoud Al-Qutayri; Baker Mohammad; Mohammad Ismail

doi:10.1109/IECON.2015.7392528

A maximally stable extremal regions system-on-chip for real-time visual surveillance

Ehab Salahat
, Hani Saleh
, Andrzej Sluzek
, Mahmoud Al-Qutayri
, Baker Mohammad
, Mohammad Ismail

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

18 Scopus citations

Abstract

This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.

Original language	British English
Title of host publication	IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	2812-2815
Number of pages	4
ISBN (Electronic)	9781479917624
DOIs	https://doi.org/10.1109/IECON.2015.7392528
State	Published - 2015
Event	41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015 - Yokohama, Japan Duration: 9 Nov 2015 → 12 Nov 2015

Publication series

Name	IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society

Conference

Conference	41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015
Country/Territory	Japan
City	Yokohama
Period	9/11/15 → 12/11/15

Keywords

ASIC
Low power Union-Find
Maximally Stable Extremal Regions
Real-time
System-on-Chip

Access to Document

10.1109/IECON.2015.7392528

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Salahat, E., Saleh, H., Sluzek, A., Al-Qutayri, M., Mohammad, B., & Ismail, M. (2015). A maximally stable extremal regions system-on-chip for real-time visual surveillance. In IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society (pp. 2812-2815). Article 7392528 (IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IECON.2015.7392528

Salahat, Ehab ; Saleh, Hani ; Sluzek, Andrzej et al. / A maximally stable extremal regions system-on-chip for real-time visual surveillance. IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 2812-2815 (IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society).

@inproceedings{6572c256162b427bbf40a65bba478fd3,

title = "A maximally stable extremal regions system-on-chip for real-time visual surveillance",

abstract = "This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31\% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.",

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author = "Ehab Salahat and Hani Saleh and Andrzej Sluzek and Mahmoud Al-Qutayri and Baker Mohammad and Mohammad Ismail",

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Salahat, E, Saleh, H, Sluzek, A, Al-Qutayri, M , Mohammad, B & Ismail, M 2015, A maximally stable extremal regions system-on-chip for real-time visual surveillance. in IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society., 7392528, IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society, Institute of Electrical and Electronics Engineers Inc., pp. 2812-2815, 41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015, Yokohama, Japan, 9/11/15. https://doi.org/10.1109/IECON.2015.7392528

A maximally stable extremal regions system-on-chip for real-time visual surveillance. / Salahat, Ehab; Saleh, Hani; Sluzek, Andrzej et al.
IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society. Institute of Electrical and Electronics Engineers Inc., 2015. p. 2812-2815 7392528 (IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents a novel implementation of the Maximally Stable Extremal Regions (MSER) detector on system-on-chip (SoC) using 65nm CMOS technology. The novel SoC was developed following the Application Specific Integrated Circuit (ASIC) design flow which significantly enhanced its realization and fabrication, and overall performances. The SoC has very low area requirement (around 0.05 mm2) and is capable of detecting both bright and dark MSERs in a single run, while computing simultaneously their associated regions' moments, simplifying its interfacing with other image algorithms (e.g. SIFT and SURF). The novel MSER SoC is power-efficient (requires 2.25 mW) and memory-efficient as it saves more than 31% of the memory space reported in the state-of-the-art MSER implementation on FPGA, making it suitable for mobile devices. With 256×256 resolution and its operating frequency of 133 MHz, the SoC is expected to have a 200 frames/second processing rate, making it suitable (when integrated with other algorithms in the system) for time-critical real-time applications such as visual surveillance.

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BT - IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015

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ER -

Salahat E, Saleh H, Sluzek A, Al-Qutayri M , Mohammad B, Ismail M. A maximally stable extremal regions system-on-chip for real-time visual surveillance. In IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society. Institute of Electrical and Electronics Engineers Inc. 2015. p. 2812-2815. 7392528. (IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society). doi: 10.1109/IECON.2015.7392528

A maximally stable extremal regions system-on-chip for real-time visual surveillance

Abstract

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Keywords

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