A low noise, low residual offset, chopped amplifier for mixed level applications

M. A.T. Sanduleanu, A. J.M. Van Tuijl, R. F. Wassenaar, M. C. Lammers, H. Wallinga

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

29 Scopus citations

Abstract

This paper describes the principle and the design of a CMOS low noise, low residual offset, chopped amplifier with a class AB output stage for noise and offset reduction in mixed analog digital applications. The operation is based on chopping and dynamic element matching to reduce noise and offset, without excessive increase of the charge injection residual offset. The main goal is to achieve low residual offsets by chopping at high frequencies reducing at the same time the 1/f noise of the amplifier. Measurements on a 0.8 μm CMOS realization show reduction of 1/f noise and 18nV/√Hz residual thermal noise at low frequencies. The residual offset is lower than 100 μV up to 8 MHz chopping frequency. Driving a 32 Ω load the linearity is better than-80 dB and better than-88 dB for a 1 kΩ load at 1 kHz.

Original languageBritish English
Title of host publicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages333-336
Number of pages4
ISBN (Electronic)0780350081
DOIs
StatePublished - 1998
Event5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal
Duration: 7 Sep 199810 Sep 1998

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume2

Conference

Conference5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
Country/TerritoryPortugal
CityLisboa
Period7/09/9810/09/98

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