A low component count series voltage compensation scheme for DFIG WTs to enhance fault ride-through capability

Bharath Babu Ambati, Parag Kanjiya, Vinod Khadkikar

Research output: Contribution to journalArticlepeer-review

49 Scopus citations


Fault ride-through (FRT) operation has been a challenge for the doubly fed induction generator (DFIG) based wind turbines (WTs) as the stator winding is directly connected to the grid. Additionally, several grid codes have been established for the grid interconnection of WTs, which demand the WT to stay connected and provide the predefined reactive current support to the grid during FRT operation. The series voltage compensation (SeVC) based FRT schemes for DFIG WTs outperforms all others in terms of smooth transient performance. However, such FRT schemes require an additional voltage-source converter (VSC) and a bulkier series transformer to provide the SeVC. This paper proposes a low component count SeVC scheme that is applicable to both individual WTs and wind parks to cope up with the recent grid codes requirements. The proposed configuration eliminates the need of a series transformer and an additional VSC for the SeVC operation with the use of three additional IGBTs/switches. Furthermore, a coordinated control strategy is proposed to control the WT that enhance its FRT capabilities. The proposed low component count FRT scheme and coordinated control strategy are validated using the detailed mathematical modeling and simulation of 1.5 MW DFIG WT.

Original languageBritish English
Article number6899676
Pages (from-to)208-217
Number of pages10
JournalIEEE Transactions on Energy Conversion
Issue number1
StatePublished - Mar 2015


  • Doubly fed induction generator (DFIG)
  • fault ride through (FRT)
  • grid faults
  • nine-switch converter
  • series voltage compensation (SeVC)
  • unbalance
  • wind turbine (WT)


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