TY - GEN
T1 - A high-throughput, contention-free low-power, Radix-2 1k,2k, 4k and 8k-point fast fourier transform engine using 28nm standard-cell process
AU - Saleh, Hani H.
AU - Mohammad, Baker S.
AU - Maalouf, Maher
PY - 2013
Y1 - 2013
N2 - This paper presents a high-throughput, contention-free, low-power, Radix-2 decimation in frequency fast Fourier transform core implemented in 28nm industry representative standard-cell process. It utilizes an algorithm to eliminate memory access contention and maximize throughput by eliminating bubbles in the butterfly's pipeline. The implementation of the FFT core is presented, including timing and place-and-route result in 28nm standard CMOS process. The FFT core can perform 1024, 2048, 4096 and 8192 points FFT. The FFT core uses two-port SRAM elements and achieves a throughput of 2-butterfly operations every clock cycle. The FFT core performs 8K-points FFT in around 40uS.
AB - This paper presents a high-throughput, contention-free, low-power, Radix-2 decimation in frequency fast Fourier transform core implemented in 28nm industry representative standard-cell process. It utilizes an algorithm to eliminate memory access contention and maximize throughput by eliminating bubbles in the butterfly's pipeline. The implementation of the FFT core is presented, including timing and place-and-route result in 28nm standard CMOS process. The FFT core can perform 1024, 2048, 4096 and 8192 points FFT. The FFT core uses two-port SRAM elements and achieves a throughput of 2-butterfly operations every clock cycle. The FFT core performs 8K-points FFT in around 40uS.
UR - http://www.scopus.com/inward/record.url?scp=84881130379&partnerID=8YFLogxK
U2 - 10.1109/DTIS.2013.6527807
DO - 10.1109/DTIS.2013.6527807
M3 - Conference contribution
AN - SCOPUS:84881130379
SN - 9781467360388
T3 - Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013
SP - 184
EP - 185
BT - Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013
T2 - 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2013
Y2 - 26 March 2013 through 28 March 2013
ER -