A High-Speed FPGA Implementation of an RSD-Based ECC Processor

Hamad Marzouqi; Mahmoud Al-Qutayri; Khaled Salah; Dimitrios Schinianakis; Thanos Stouraitis

doi:10.1109/TVLSI.2015.2391274

A High-Speed FPGA Implementation of an RSD-Based ECC Processor

Hamad Marzouqi
, Mahmoud Al-Qutayri
, Khaled Salah
, Dimitrios Schinianakis
, Thanos Stouraitis

Computer & Communication Engineering

University of Patras

Research output: Contribution to journal › Article › peer-review

80 Scopus citations

Abstract

In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-point multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.

Original language	British English
Article number	7027194
Pages (from-to)	151-164
Number of pages	14
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	24
Issue number	1
DOIs	https://doi.org/10.1109/TVLSI.2015.2391274
State	Published - Jan 2016

Keywords

Application-specific instruction-set processor (ASIP)
elliptic curve cryptography (ECC)
field-programmable gate array (FPGA)
Karatsuba-Ofman multiplication
redundant signed digit (RSD)

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10.1109/TVLSI.2015.2391274

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abstract = "In this paper, an exportable application-specific instruction-set elliptic curve cryptography processor based on redundant signed digit representation is proposed. The processor employs extensive pipelining techniques for Karatsuba-Ofman method to achieve high throughput multiplication. Furthermore, an efficient modular adder without comparison and a high-throughput modular divider, which results in a short datapath for maximized frequency, are implemented. The processor supports the recommended NIST curve P256 and is based on an extended NIST reduction scheme. The proposed processor performs single-point multiplication employing points in affine coordinates in 2.26 ms and runs at a maximum frequency of 160 MHz in Xilinx Virtex 5 (XC5VLX110T) field-programmable gate array.",

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A High-Speed FPGA Implementation of an RSD-Based ECC Processor

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Keywords

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