A hierarchical cost estimation technique for high level synthesis

Mahmoud Meribout, Masato Motomura

Research output: Contribution to journalArticlepeer-review


The aim of this paper is to present a new cost estimation technique to synthesis hardware from high level circuit description. The scheduling and allocation processes are performed in alternative manner, while using realistic cost measurements models that account for Functional Unit (FU), registers, and multiplexers. This is an improvement over previous works, were most of them use very simple cost models that primarily focus on FU resources alone. These latest, however, are not accurate enough to allow effective design space exploration since the effects of storage and interconnect resources can indeed dominates the cost function. We tested our technique on several high-level synthesis benchmarks. The results indicate that the tool can generate near-optimal bus-based and multiplexer-based architectural models with lower number of registers and buses, while presenting high throughput.

Original languageBritish English
Pages (from-to)444-461
Number of pages18
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number2
StatePublished - Feb 2003


  • Allocation
  • Bus-based architecture
  • Hardware cost estimation
  • High level synthesis
  • Multiplexer-based architecture
  • Partitioning
  • Scheduling


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