A hardware accelerator for real-time extraction of the linear-time MSER algorithm

Sohailah Alyammahi, Ehab Salahat, Hani Saleh, Andrzej Sluzek

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

This paper presents a novel hardware accelerator architecture for the linear-time Maximally Stable Extremal Regions (MSER) detector algorithm. In contrast to the standard MSER algorithm, the linear-time MSER implementation is more suitable for real-time applications of image retrieval in large-scale and high resolution datasets (e.g. satellite images). The linear-time MSER accelerator design is optimized by enhancing its flooding process (which is one of the major drawbacks of the standard linear-time MSER) using a structure that we called stack of pointers, which makes it memory-efficient as it reduces the memory requirement by nearly 90%. The accelerator is configurable and can be integrated with many image processing algorithms, allowing a wide spectrum of potential real-time applications to be realized even on small and power-limited devices.

Original languageBritish English
Title of host publicationIECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages65-69
Number of pages5
ISBN (Electronic)9781479917624
DOIs
StatePublished - 2015
Event41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015 - Yokohama, Japan
Duration: 9 Nov 201512 Nov 2015

Publication series

NameIECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society

Conference

Conference41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015
Country/TerritoryJapan
CityYokohama
Period9/11/1512/11/15

Keywords

  • ASIC
  • Hardware Accelerators
  • Linear-time MSER
  • Maximally Stable Extremal Regions
  • System-on-Chip

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