A frequency synthesizer based on zero-crossing digital phaselocked loop

Ehab Salahat; Saleh R. Al-Araji; Mahmoud Al-Qutayri

doi:10.1109/ICECS.2013.6815544

A frequency synthesizer based on zero-crossing digital phaselocked loop

Ehab Salahat
, Saleh R. Al-Araji
, Mahmoud Al-Qutayri

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.

Original language	British English
Title of host publication	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	835-838
Number of pages	4
ISBN (Print)	9781479924523
DOIs	https://doi.org/10.1109/ICECS.2013.6815544
State	Published - 2013
Event	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 - Abu Dhabi, United Arab Emirates Duration: 8 Dec 2013 → 11 Dec 2013

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference	2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	8/12/13 → 11/12/13

Keywords

Finite State Machine
Frequency Synthesizers
Hybrid Divider
Zero-Crossing Digital Phaselocked Loop

Access to Document

10.1109/ICECS.2013.6815544

Cite this

Salahat, E., Al-Araji, S. R., & Al-Qutayri, M. (2013). A frequency synthesizer based on zero-crossing digital phaselocked loop. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 (pp. 835-838). Article 6815544 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2013.6815544

Salahat, Ehab ; Al-Araji, Saleh R. ; Al-Qutayri, Mahmoud. / A frequency synthesizer based on zero-crossing digital phaselocked loop. 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc., 2013. pp. 835-838 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

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title = "A frequency synthesizer based on zero-crossing digital phaselocked loop",

abstract = "This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.",

keywords = "Finite State Machine, Frequency Synthesizers, Hybrid Divider, Zero-Crossing Digital Phaselocked Loop",

author = "Ehab Salahat and Al-Araji, \{Saleh R.\} and Mahmoud Al-Qutayri",

year = "2013",

doi = "10.1109/ICECS.2013.6815544",

language = "British English",

isbn = "9781479924523",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "835--838",

booktitle = "2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013",

address = "United States",

note = "2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 ; Conference date: 08-12-2013 Through 11-12-2013",

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Salahat, E, Al-Araji, SR & Al-Qutayri, M 2013, A frequency synthesizer based on zero-crossing digital phaselocked loop. in 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013., 6815544, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Institute of Electrical and Electronics Engineers Inc., pp. 835-838, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013, Abu Dhabi, United Arab Emirates, 8/12/13. https://doi.org/10.1109/ICECS.2013.6815544

A frequency synthesizer based on zero-crossing digital phaselocked loop. / Salahat, Ehab; Al-Araji, Saleh R.; Al-Qutayri, Mahmoud.
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc., 2013. p. 835-838 6815544 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Salahat, Ehab

AU - Al-Araji, Saleh R.

AU - Al-Qutayri, Mahmoud

PY - 2013

Y1 - 2013

N2 - This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.

AB - This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.

KW - Finite State Machine

KW - Frequency Synthesizers

KW - Hybrid Divider

KW - Zero-Crossing Digital Phaselocked Loop

UR - https://www.scopus.com/pages/publications/84901475094

U2 - 10.1109/ICECS.2013.6815544

DO - 10.1109/ICECS.2013.6815544

M3 - Conference contribution

AN - SCOPUS:84901475094

SN - 9781479924523

T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

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BT - 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013

Y2 - 8 December 2013 through 11 December 2013

ER -

Salahat E, Al-Araji SR, Al-Qutayri M. A frequency synthesizer based on zero-crossing digital phaselocked loop. In 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013. Institute of Electrical and Electronics Engineers Inc. 2013. p. 835-838. 6815544. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.2013.6815544

A frequency synthesizer based on zero-crossing digital phaselocked loop

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