A frequency synthesizer based on zero-crossing digital phaselocked loop

Ehab Salahat, Saleh R. Al-Araji, Mahmoud Al-Qutayri

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

This paper presents an efficient hybrid frequency synthesizer, that is capable of both integer and fractional division, design based on the Zero-Crossing Digital Phase-locked Loop architecture. The design uses an efficient adaptation mechanism to maintain the in-lock state following the division process. The fast switching, locking and acquisition of the system make it an excellent candidate for synthesis even in Doppler environment. The simulation results demonstrate that the proposed synthesizer can achieve the desired frequency division.

Original languageBritish English
Title of host publication2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages835-838
Number of pages4
ISBN (Print)9781479924523
DOIs
StatePublished - 2013
Event2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013 - Abu Dhabi, United Arab Emirates
Duration: 8 Dec 201311 Dec 2013

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

Conference2013 IEEE 20th International Conference on Electronics, Circuits, and Systems, ICECS 2013
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period8/12/1311/12/13

Keywords

  • Finite State Machine
  • Frequency Synthesizers
  • Hybrid Divider
  • Zero-Crossing Digital Phaselocked Loop

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