A floating-point fused add-subtract unit

Hani Saleh; Earl E. Swartzlander

doi:10.1109/MWSCAS.2008.4616850

A floating-point fused add-subtract unit

Hani Saleh, Earl E. Swartzlander

Electrical Engineering

The University of Texas at Austin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

34 Scopus citations

Abstract

A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.

Original language	British English
Title of host publication	2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Pages	519-522
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2008.4616850
State	Published - 2008
Event	2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS - Knoxville, TN, United States Duration: 10 Aug 2008 → 13 Aug 2008

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Conference

Conference	2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Country/Territory	United States
City	Knoxville, TN
Period	10/08/08 → 13/08/08

Access to Document

10.1109/MWSCAS.2008.4616850

Cite this

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title = "A floating-point fused add-subtract unit",

abstract = "A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.",

author = "Hani Saleh and Swartzlander, {Earl E.}",

year = "2008",

doi = "10.1109/MWSCAS.2008.4616850",

language = "British English",

isbn = "9781424421671",

series = "Midwest Symposium on Circuits and Systems",

pages = "519--522",

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note = "2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS ; Conference date: 10-08-2008 Through 13-08-2008",

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Saleh, H & Swartzlander, EE 2008, A floating-point fused add-subtract unit. in 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS., 4616850, Midwest Symposium on Circuits and Systems, pp. 519-522, 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS, Knoxville, TN, United States, 10/08/08. https://doi.org/10.1109/MWSCAS.2008.4616850

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AU - Swartzlander, Earl E.

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N2 - A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.

AB - A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.

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U2 - 10.1109/MWSCAS.2008.4616850

DO - 10.1109/MWSCAS.2008.4616850

M3 - Conference contribution

AN - SCOPUS:54249095241

SN - 9781424421671

T3 - Midwest Symposium on Circuits and Systems

SP - 519

EP - 522

BT - 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS

T2 - 2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS

Y2 - 10 August 2008 through 13 August 2008

ER -

A floating-point fused add-subtract unit

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