A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

Adnan Suleiman; Hani Saleh; Adel Hussein; David Akopian

doi:10.1109/ICCD.2008.4751880

A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

Adnan Suleiman, Hani Saleh, Adel Hussein, David Akopian

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024- point FFT with 2 processing elements using 45nm process technology, including area, timing, power and place-and-route results.

Original language	British English
Title of host publication	26th IEEE International Conference on Computer Design 2008, ICCD
Pages	321-327
Number of pages	7
DOIs	https://doi.org/10.1109/ICCD.2008.4751880
State	Published - 2008
Event	26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States Duration: 12 Oct 2008 → 15 Oct 2008

Publication series

Name	26th IEEE International Conference on Computer Design 2008, ICCD

Conference

Conference	26th IEEE International Conference on Computer Design 2008, ICCD
Country/Territory	United States
City	Lake Tahoe, CA
Period	12/10/08 → 15/10/08

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10.1109/ICCD.2008.4751880

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Suleiman, A., Saleh, H., Hussein, A., & Akopian, D. (2008). A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 321-327). Article 4751880 (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751880

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title = "A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications",

abstract = "The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024- point FFT with 2 processing elements using 45nm process technology, including area, timing, power and place-and-route results.",

author = "Adnan Suleiman and Hani Saleh and Adel Hussein and David Akopian",

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doi = "10.1109/ICCD.2008.4751880",

language = "British English",

isbn = "9781424426584",

series = "26th IEEE International Conference on Computer Design 2008, ICCD",

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note = "26th IEEE International Conference on Computer Design 2008, ICCD ; Conference date: 12-10-2008 Through 15-10-2008",

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Suleiman, A, Saleh, H, Hussein, A & Akopian, D 2008, A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications. in 26th IEEE International Conference on Computer Design 2008, ICCD., 4751880, 26th IEEE International Conference on Computer Design 2008, ICCD, pp. 321-327, 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, United States, 12/10/08. https://doi.org/10.1109/ICCD.2008.4751880

A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications. / Suleiman, Adnan; Saleh, Hani; Hussein, Adel et al.
26th IEEE International Conference on Computer Design 2008, ICCD. 2008. p. 321-327 4751880 (26th IEEE International Conference on Computer Design 2008, ICCD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The paper presents a family of architectures for FFT implementation based on the decomposition of the perfect shuffle permutation, which can be designed with variable number of processing elements. This provides designers with a trade-off choice of speed vs. complexity (cost and area.). A detailed case study is provided on the implementation of 1024- point FFT with 2 processing elements using 45nm process technology, including area, timing, power and place-and-route results.

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A Family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

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