TY - GEN
T1 - A contention-free Radix-2 8k-point fast Fourier Transform engine using single port SRAMs
AU - Saleh, Hani
AU - Swartzlander, Earl E.
PY - 2008
Y1 - 2008
N2 - This paper presents a Radix-2 decimation in frequency fast Fourier transform engine that is based on a switch based architecture. The architecture interconnects M processing elements with 2*M memories. An algorithm to eliminate memory access contention is presented. The implementation of an 8192-point FFT with 2 processing elements is presented, including timing and place-and-route results. The length of the FFT can be easily changed to integer powers of 2 from 64 to 8192 points. The switch based architecture provides a factor of M speedup over a single processing element realization. The architecture uses single-port memories and achievesa throughput of roughly 1 GSPS (66% of the throughput of dual-ported SRAM based implementations) .
AB - This paper presents a Radix-2 decimation in frequency fast Fourier transform engine that is based on a switch based architecture. The architecture interconnects M processing elements with 2*M memories. An algorithm to eliminate memory access contention is presented. The implementation of an 8192-point FFT with 2 processing elements is presented, including timing and place-and-route results. The length of the FFT can be easily changed to integer powers of 2 from 64 to 8192 points. The switch based architecture provides a factor of M speedup over a single processing element realization. The architecture uses single-port memories and achievesa throughput of roughly 1 GSPS (66% of the throughput of dual-ported SRAM based implementations) .
UR - https://www.scopus.com/pages/publications/50149099662
U2 - 10.1109/SECON.2008.4494345
DO - 10.1109/SECON.2008.4494345
M3 - Conference contribution
AN - SCOPUS:50149099662
SN - 9781424418848
T3 - Conference Proceedings - IEEE SOUTHEASTCON
SP - 497
EP - 502
BT - IEEE SoutheastCon 2008
T2 - IEEE SoutheastCon 2008
Y2 - 3 April 2008 through 6 April 2008
ER -