A Comprehensive Analysis of Enhanced DC-Bus Utilization and Reduced Component Count Five-Level Inverter for PV-Grid Integration

Several five-level inverters have limitations, such as low DC-bus voltage utilization and a large number of components. This paper describes a new five-level inverter with a switched capacitor design that aims to address these issues by maximizing the utilization of the DC bus voltage while reducing the component count. The proposed topology includes six active switches, two diodes, a floating capacitor, and a single DC source, with a 50% reduction in bus voltage requirements compared to traditional designs. The level-shifted sine pulse width modulation is employed to produce the switching pulses for the proposed inverter. Following the theoretical analysis, the actual behavior of the switching devices is validated via real-time implementation with the OPALRT 5700 real-time emulator. The superiority of the proposed inverter is tested under various steady-state and dynamic conditions to demonstrate its effectiveness under single-phase open-loop and three-phase photovoltaic (PV)-grid integrated conditions using a comparative analysis. The proposed inverter has a maximum efficiency of 97.75% and output voltage distortion of 26.61%, making it ideal for PV applications.