A Cascaded Nine-Level Inverter Topology with T-Type and H-Bridge with Increased DC-Bus Utilization

Souradeep Pal, Mriganka Ghosh Majumder, R. Rakesh, K. Gopakumar, Loganathan Umanand, Dariusz Zielinski, Abdul R. Beig

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

This article introduces a hybrid nine-level inverter topology with extended dc-bus utilization for operation at over modulation range without the presence of lower order harmonics (predominantly fifth and seventh) when compared to conventional two-level and multilevel inverter with hexagonal voltage space vector structure. The proposed inverter is a cascade of a five-level T-type unit and an H-bridge (HB) unit. An increase in the dc-bus utilization is possible by increasing the pole voltage levels to \pm (V_{\text{dc}}/2+V_{\text{dc}}/8) using the HB capacitor voltage and also the capacitor voltages are balanced by adding a offset to sine reference. The aforementioned pulsewidth modulation strategy allows us to increase the peak phase fundamental voltage from 0.577V_{\text{dc}} to 0.625V_{\text{dc}} in case of unity power factor (p.f) load and to 0.637V_{\text{dc}} for 0.82 p.f load with the proposed nine-level inverter. The limiting factor on increasing the dc bus utilization such as p.f, HB capacitor balancing are analysed broadly in this article. The proposed inverter scheme and its claim of increasing the peak phase fundamental voltage is experimentally validated in a laboratory prototype.

Original languageBritish English
Article number9119149
Pages (from-to)285-294
Number of pages10
JournalIEEE Transactions on Power Electronics
Volume36
Issue number1
DOIs
StatePublished - Jan 2021

Keywords

  • Common mode offset
  • induction motor (IM) drive
  • nine-level inverter
  • pulsewidth modulation (PWM)

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