A CAD methodology for the characterization of wide on-chip buses

I. M. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, H. Smith

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design eycle. The modeling is based on a manufacturing (rather than design-mauual) description of the back-end-of-theline (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data-bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to waluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current returnpath resistance on frequencies. The CAD metbodology described in this paper has been extensively correlated with on-chip hardware measurements.

Original languageBritish English
Title of host publicationElectrical Performance of Electronic Packaging
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)0780381289, 9780780381285
StatePublished - 2003
EventElectrical Performance of Electronic Packaging, 2003 - Princeton, United States
Duration: 27 Oct 200329 Oct 2003

Publication series

NameElectrical Performance of Electronic Packaging


ConferenceElectrical Performance of Electronic Packaging, 2003
Country/TerritoryUnited States


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