TY - GEN
T1 - A CAD methodology and tool for the characterization of wide on-chip buses
AU - Elfadel, I. M.
AU - Deutsch, A.
AU - Kopcsay, G.
AU - Rubin, B.
AU - Smith, H.
PY - 2004
Y1 - 2004
N2 - In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.
AB - In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.
UR - http://www.scopus.com/inward/record.url?scp=84893748361&partnerID=8YFLogxK
U2 - 10.1109/DATE.2004.1269221
DO - 10.1109/DATE.2004.1269221
M3 - Conference contribution
AN - SCOPUS:84893748361
SN - 0769520855
SN - 9780769520858
T3 - Proceedings -Design, Automation and Test in Europe, DATE
SP - 144
EP - 149
BT - Design, Automation and Test in Europe Conference and Exhibition, DATE 2004
T2 - Design, Automation and Test in Europe Conference and Exhibition, DATE 2004
Y2 - 16 February 2004 through 20 February 2004
ER -