A CAD methodology and tool for the characterization of wide on-chip buses

I. M. Elfadel, A. Deutsch, G. Kopcsay, B. Rubin, H. Smith

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we describe a CAD methodology for the full electrical characterization of high-performance, on-chip data buses. The goal of this methodology is to allow the accurate modeling and analysis of wide, on-chip data buses as early as possible in the design cycle. The modeling is based on a manufacturing (rather than design-manual) description of the back-end-of-the-line (BEOL) cross section of a given technology and on a full yet contained description of the power-ground mesh in which the data bus is embedded. One major aspect of the resulting electrical models is that they allow the designer to evaluate the wide bus from the three viewpoints of signal timing, crosstalk (both inductive and capacitive), and common-mode signal integrity. Another major aspect is that they take into account such important high-frequency phenomena as the dependence of the current return-path resistance on frequencies. The CAD methodology described in this paper has been extensively correlated with on-chip hardware measurements.

Original languageBritish English
Title of host publicationDesign, Automation and Test in Europe Conference and Exhibition, DATE 2004
Pages144-149
Number of pages6
DOIs
StatePublished - 2004
EventDesign, Automation and Test in Europe Conference and Exhibition, DATE 2004 - Paris, France
Duration: 16 Feb 200420 Feb 2004

Publication series

NameProceedings -Design, Automation and Test in Europe, DATE
Volume3
ISSN (Print)1530-1591

Conference

ConferenceDesign, Automation and Test in Europe Conference and Exhibition, DATE 2004
Country/TerritoryFrance
CityParis
Period16/02/0420/02/04

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