TY - JOUR
T1 - A 93% peak efficiency fully-integrated multilevel multistate hybrid DC-DC converter
AU - Abdulslam, Abdullah
AU - Mohammad, Baker
AU - Ismail, Mohammed
AU - Mercier, Patrick P.
AU - Ismail, Yehea
N1 - Funding Information:
Manuscript received March 5, 2017; revised June 20, 2017, September 10, 2017, and December 6, 2017; accepted December 29, 2017. Date of publication January 31, 2018; date of current version July 3, 2018. This work was supported in part by the Zewail City of Science and Technology, in part by AUC, in part by Khalifa University, in part by SRC, in part by STDF, in part by Intel, in part by Mentor Graphics, in part by ITIDA, in part by ASRF, in part by MCIT, and in part by the ATIC-SRC under Contract 2013-HJ-2440. This paper was recommended by Associate Editor H. Lee. (Corresponding author: Abdullah Abdulslam.) A. Abdulslam and P. P. Mercier are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92037 USA (e-mail: [email protected]; [email protected]).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/8
Y1 - 2018/8
N2 - The general structure of a multilevel multistate dc-dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub-μs range with output voltage ripples below 50 mV.
AB - The general structure of a multilevel multistate dc-dc converter is introduced, which is a hybrid between inductor-based (buck) converters and capacitor-based (switched capacitor) converters. The control of the new converter is hybrid between switched capacitor converters and buck converters, where the coarse tuning of the output voltage is achieved through the selection of an appropriate operating region similar to an SC converter, while fine tuning is achieved through the adjustment of a duty cycle value similar to a buck converter. A silicon implementation of a four-level four-state hybrid converter is presented as a specific example of the general hybrid converter structure. A new state interleaving technique was employed resulting in an increased effective switching frequency of the converter. Silicon measurements of the integrated four-level four-state converter on a 65-nm GF technology show that the converter can cover a wide range of output voltage values achieving a peak efficiency of 93% with a power density of 47 mW/mm2. The implemented converter attains a response time in the sub-μs range with output voltage ripples below 50 mV.
KW - 4-level
KW - buck converters
KW - DC-DC power converters
KW - DVFS
KW - hybrid converter
KW - integrated converters
KW - multilevel
KW - switched capacitor converters
UR - http://www.scopus.com/inward/record.url?scp=85041427747&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2018.2793163
DO - 10.1109/TCSI.2018.2793163
M3 - Article
AN - SCOPUS:85041427747
SN - 1057-7122
VL - 65
SP - 2617
EP - 2630
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 8
ER -