A 65nm level-1 cache for mobile applications

Baker Mohammad, Ken Lin, Paul Bassett, Adnan Aziz

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations


We describe L1 cache designed for QUALCOMM®'s latest-generation digital signal processor (DSP) core. The cache is 32KB with variable associativity (4 to 16 ways) and is pseudo-dual-ported. Dual access is achieved by banking the cache in a way that minimizes bank conflict to less than 1%. The cache operates at 600 MHZ under worst-case PVT conditions and dissipates 100.8 pJoule per access at 1.2V. A low-leakage multi-threshold-voltage (MTV) 65nm foundry process technology [10,11] is used for fabrication. The cache supports simultaneous dual double-word access, and four-double-word evict and fill operations. The memory system includes a tag array and data array: both are designed using QUALCOMM®'s defined single-ported 6T SRAM cell, with an area of 0.54 mm 2 and leakage per cell of less than 10 pA. Three threshold voltages are used with foot and head switches to trade off leakage, active power, and performance. The design of the tag and data array uses novel circuit approaches to enable high coverage on testability through data bypassing with minimum impact to speed. It also employs self-timed circuit with process-dependent sense-amp tracking for high speed and low power.

Original languageBritish English
Title of host publicationICM'08 - 20th International Conference on Microelectronics
Number of pages6
StatePublished - 2008
Event20th International Conference on Microelectronics, ICM'08 - Sharjah, United Arab Emirates
Duration: 14 Dec 200817 Dec 2008

Publication series

NameProceedings of the International Conference on Microelectronics, ICM


Conference20th International Conference on Microelectronics, ICM'08
Country/TerritoryUnited Arab Emirates


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