A 65nm ASIC design for measuring mental stress from the heart rate variations

Huda Goian, Aamna Alali, Temesghen Habte, Hani Saleh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Stress become a routine and part of human life. It can keep the person enthusiastic and energetic. However, unmanageable stress could be deathly. The main consideration of this paper is to represent a new ASIC design for stress recognition algorithm based on detection of the stress signs. In fact, plenty of information could be extracted from the heart signal for multiple illnesses which make it reliable and more convenience to be used [3]. Thus, in this framework, Heart Rate Variability (HRV) is used in distinguishing among the stress levels such as low stress, moderate stress, and high stress. Two stage SVM classifiers were used and it achieved 96.4% accuracy in the first stage and 80.5% in the second stage. The system consumed a total area of 0.073 mm2 and a consumed power of 33.4845uW.

Original languageBritish English
Title of host publicationICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages334-338
Number of pages5
ISBN (Electronic)9781538619117
DOIs
StatePublished - 14 Feb 2018
Event24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017 - Batumi, Georgia
Duration: 5 Dec 20178 Dec 2017

Publication series

NameICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
Volume2018-January

Conference

Conference24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017
Country/TerritoryGeorgia
CityBatumi
Period5/12/178/12/17

Keywords

  • ASIC design
  • Electrocardiogram signal
  • HRV
  • Stress detection
  • Support Vector Machine

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