@inproceedings{099eae59d7134579a0b510fad0d4d13b,
title = "A 65nm ASIC based 256 NIST prime field ECC processor",
abstract = "This paper presents a 65nm ASIC based 256 NIST prime field ECC processor. To achieve high throughput, extensive pipelining techniques were applied to realize the Karatsuba- Ofman Multiplier along with enhanced NIST Reduction Formula. The processor architecture was implemented using Global Foundry 65nm Low Power (LPE) technology. The processor runs at a maximum frequency of 244 MHz and performs single scalar point multiplication within 1.48 ms. The processor occupies 0.472 mm 2 die area with 114 kgates and consumes a maximum power of 6.8 mW. Further to ASIC implementation, the processor was prototyped using a FPGA Virtex 5 device exhibited a throughput improvement of 140% over previously published results. Both ASIC and FPGA implementations showed competitive results when compared with state of the art ECC processors found in the literature.",
keywords = "CMOS, Elliptic curve cryptography, FPGA, Karatsuba-ofman multiplication, Redundant signed digit",
author = "Hamad Marzouqi and Mahmoud Al-Qutayri and Khaled Salah and Hani Saleh",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 ; Conference date: 16-10-2016 Through 19-10-2016",
year = "2016",
month = jul,
day = "2",
doi = "10.1109/MWSCAS.2016.7870035",
language = "British English",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016",
address = "United States",
}