TY - GEN
T1 - A 65-nm pulsed latch with a single clocked transistor
AU - Saint-Laurent, Martin
AU - Mohammad, Baker
AU - Bassett, Paul
PY - 2007
Y1 - 2007
N2 - This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are locally distributed to a group of latches. Finally, the paper discusses how to further reduce the dynamic clock power consumption of the new latch without degrading its timing by feeding it a low-swing clock.
AB - This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are locally distributed to a group of latches. Finally, the paper discusses how to further reduce the dynamic clock power consumption of the new latch without degrading its timing by feeding it a low-swing clock.
KW - Low voltage swing
KW - Minimum clock power
KW - Pulsed latch
KW - Virtual-ground clocking
UR - https://www.scopus.com/pages/publications/36949006685
U2 - 10.1145/1283780.1283855
DO - 10.1145/1283780.1283855
M3 - Conference contribution
AN - SCOPUS:36949006685
SN - 1595937099
SN - 9781595937094
T3 - Proceedings of the International Symposium on Low Power Electronics and Design
SP - 347
EP - 350
BT - ISLPED'07
T2 - ISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Y2 - 27 August 2007 through 29 August 2007
ER -