A 65-nm pulsed latch with a single clocked transistor

Martin Saint-Laurent, Baker Mohammad, Paul Bassett

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are locally distributed to a group of latches. Finally, the paper discusses how to further reduce the dynamic clock power consumption of the new latch without degrading its timing by feeding it a low-swing clock.

Original languageBritish English
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages347-350
Number of pages4
DOIs
StatePublished - 2007
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: 27 Aug 200729 Aug 2007

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Conference

ConferenceISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/TerritoryUnited States
CityPortland, OR
Period27/08/0729/08/07

Keywords

  • Low voltage swing
  • Minimum clock power
  • Pulsed latch
  • Virtual-ground clocking

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