A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI

M. A.T. Sanduleanu, S. Reynolds, J. O. Plouchart

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

A 4GS/s sampling system achieved 8.45-ENOB linearity with 5.7fJ/conversion energy efficiency at 1V power supply and its gain can be adjusted in a digital manner. The measured IIP3 and IIP2 are 17.7dBm and 40dBm respectively. The ENOB of the sampler shows no degradation up to Nyquist frequency. An integrated phase rotator allows digital clock delay and duty cycle adjustment with sub-picosecond resolution. The sampling system tracks and settles in 1/4UI (62.5ps). Realized in a 45nm SOI CMOS the active area of the sampler is only 0.2×0.2mm2.

Original languageBritish English
Title of host publication2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs
StatePublished - 2011
Event33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States
Duration: 19 Sep 201121 Sep 2011

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

Conference33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Country/TerritoryUnited States
CitySan Jose, CA
Period19/09/1121/09/11

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