A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications

Martin Saint-Laurent; Paul Bassett; Ken Lin; Baker Mohammad; Yuhe Wang; Xufeng Chen; Maen Alradaideh; Tom Wernimont; Kartik Ayyar; Dan Bui; Dwight Galbi; Allan Lester; Marzio Pedrali-Noy; Willie Anderson

doi:10.1109/JSSC.2014.2371454

A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications

Martin Saint-Laurent
, Paul Bassett
, Ken Lin
, Baker Mohammad
, Yuhe Wang
, Xufeng Chen
, Maen Alradaideh
, Tom Wernimont
, Kartik Ayyar
, Dan Bui
, Dwight Galbi
, Allan Lester
, Marzio Pedrali-Noy
, Willie Anderson

Electrical Engineering

Qualcomm Incorporated

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.

Original language	British English
Article number	6983635
Pages (from-to)	81-91
Number of pages	11
Journal	IEEE Journal of Solid-State Circuits
Volume	50
Issue number	1
DOIs	https://doi.org/10.1109/JSSC.2014.2371454
State	Published - 12 Dec 2015

Keywords

Capacitor-less LDO
clock power reduction
DSP
leakage optimization
low power design
near-threshold computing
power gating
pulsed latches

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/JSSC.2014.2371454

Cite this

Saint-Laurent, M., Bassett, P., Lin, K., Mohammad, B., Wang, Y., Chen, X., Alradaideh, M., Wernimont, T., Ayyar, K., Bui, D., Galbi, D., Lester, A., Pedrali-Noy, M., & Anderson, W. (2015). A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications. IEEE Journal of Solid-State Circuits, 50(1), 81-91. Article 6983635. https://doi.org/10.1109/JSSC.2014.2371454

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title = "A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications",

abstract = "This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.",

keywords = "Capacitor-less LDO, clock power reduction, DSP, leakage optimization, low power design, near-threshold computing, power gating, pulsed latches",

author = "Martin Saint-Laurent and Paul Bassett and Ken Lin and Baker Mohammad and Yuhe Wang and Xufeng Chen and Maen Alradaideh and Tom Wernimont and Kartik Ayyar and Dan Bui and Dwight Galbi and Allan Lester and Marzio Pedrali-Noy and Willie Anderson",

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Saint-Laurent, M, Bassett, P, Lin, K, Mohammad, B, Wang, Y, Chen, X, Alradaideh, M, Wernimont, T, Ayyar, K, Bui, D, Galbi, D, Lester, A, Pedrali-Noy, M & Anderson, W 2015, 'A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications', IEEE Journal of Solid-State Circuits, vol. 50, no. 1, 6983635, pp. 81-91. https://doi.org/10.1109/JSSC.2014.2371454

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T1 - A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications

AU - Saint-Laurent, Martin

AU - Bassett, Paul

AU - Lin, Ken

AU - Mohammad, Baker

AU - Wang, Yuhe

AU - Chen, Xufeng

AU - Alradaideh, Maen

AU - Wernimont, Tom

AU - Ayyar, Kartik

AU - Bui, Dan

AU - Galbi, Dwight

AU - Lester, Allan

AU - Pedrali-Noy, Marzio

AU - Anderson, Willie

PY - 2015/12/12

Y1 - 2015/12/12

N2 - This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.

AB - This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.

KW - Capacitor-less LDO

KW - clock power reduction

KW - DSP

KW - leakage optimization

KW - low power design

KW - near-threshold computing

KW - power gating

KW - pulsed latches

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DO - 10.1109/JSSC.2014.2371454

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VL - 50

SP - 81

EP - 91

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 1

M1 - 6983635

ER -

A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications

Abstract

Keywords

UN SDGs

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