Abstract
This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.
Original language | British English |
---|---|
Article number | 6983635 |
Pages (from-to) | 81-91 |
Number of pages | 11 |
Journal | IEEE Journal of Solid-State Circuits |
Volume | 50 |
Issue number | 1 |
DOIs | |
State | Published - 12 Dec 2015 |
Keywords
- Capacitor-less LDO
- clock power reduction
- DSP
- leakage optimization
- low power design
- near-threshold computing
- power gating
- pulsed latches