A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications

Martin Saint-Laurent, Paul Bassett, Ken Lin, Baker Mohammad, Yuhe Wang, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Marzio Pedrali-Noy, Willie Anderson

Research output: Contribution to journalArticlepeer-review

15 Scopus citations

Abstract

This paper describes the implementation of a Qualcomm Hexagon digital signal processor (DSP) in a 28 nm high-κ metal gate technology. The DSP is a multi-threaded very-long- instruction-word (VLIW) machine optimized for low leakage and energy efficiency. It uses a clock distribution network, clock gating cells, and pulsed latches that are optimized for low switching energy. The processor can be powered using a low-dropout (LDO) voltage regulator or a head switch. It operates from 255 MHz at 0.60 V to 1.24 GHz at 1.05 V. When operating from the LDO, the power consumption of the core can be as low as 58 μW/MHz, which is two to three times lower than comparable cores optimized for ultra-low voltage operation.

Original languageBritish English
Article number6983635
Pages (from-to)81-91
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume50
Issue number1
DOIs
StatePublished - 12 Dec 2015

Keywords

  • Capacitor-less LDO
  • clock power reduction
  • DSP
  • leakage optimization
  • low power design
  • near-threshold computing
  • power gating
  • pulsed latches

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