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3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect

  • New York University

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a flash Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125 GS/s with 4.9 ENOB and a Walden figure of merit of 109 fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2 mW from a 1 V supply. It was realized in the 45 nm PDSOI from Global Foundries.

Original languageBritish English
Title of host publicationVLSI-SoC 2023
Subtitle of host publicationInnovations for Trustworthy Artificial Intelligence - 31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Revised Extended Selected Papers
EditorsIbrahim (Abe) M. Elfadel, Lutfi Albasha
PublisherSpringer Science and Business Media Deutschland GmbH
Pages237-248
Number of pages12
ISBN (Print)9783031709463
DOIs
StatePublished - 2024
Event31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, VLSI-SoC 2023 - Dubai, United Arab Emirates
Duration: 16 Oct 202318 Oct 2023

Publication series

NameIFIP Advances in Information and Communication Technology
Volume680 IFIPAICT
ISSN (Print)1868-4238
ISSN (Electronic)1868-422X

Conference

Conference31st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration - System on a Chip, VLSI-SoC 2023
Country/TerritoryUnited Arab Emirates
CityDubai
Period16/10/2318/10/23

Keywords

  • Backplane interconnect
  • Gigabit Radio
  • mm-Waves
  • Sampler
  • Time-Domain ADC
  • Track and Hold

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