3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect

Solomon Serunjogi; Mihai Sanduleanu

doi:10.1109/VLSI-SoC57769.2023.10321875

3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect

Solomon Serunjogi, Mihai Sanduleanu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125GS/s with 4.9 ENOB and a Walden figure of merit of 109fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2mW from a 1V supply. It was realized in the 45nm PDSOI from Global Foundries.

Original language	British English
Title of host publication	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023
Publisher	IEEE Computer Society
ISBN (Electronic)	9798350325997
DOIs	https://doi.org/10.1109/VLSI-SoC57769.2023.10321875
State	Published - 2023
Event	31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 - Dubai, United Arab Emirates Duration: 16 Oct 2023 → 18 Oct 2023

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023
Country/Territory	United Arab Emirates
City	Dubai
Period	16/10/23 → 18/10/23

Keywords

Backplane interconnect
Gigabit Radio
mm-Waves
Sampler
Time-Domain ADC
Track and Hold

Access to Document

10.1109/VLSI-SoC57769.2023.10321875

Cite this

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title = "3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect",

abstract = "This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125GS/s with 4.9 ENOB and a Walden figure of merit of 109fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2mW from a 1V supply. It was realized in the 45nm PDSOI from Global Foundries.",

keywords = "Backplane interconnect, Gigabit Radio, mm-Waves, Sampler, Time-Domain ADC, Track and Hold",

author = "Solomon Serunjogi and Mihai Sanduleanu",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023 ; Conference date: 16-10-2023 Through 18-10-2023",

year = "2023",

doi = "10.1109/VLSI-SoC57769.2023.10321875",

language = "British English",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

publisher = "IEEE Computer Society",

booktitle = "2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023",

address = "United States",

}

Serunjogi, S & Sanduleanu, M 2023, 3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect. in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 31st IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2023, Dubai, United Arab Emirates, 16/10/23. https://doi.org/10.1109/VLSI-SoC57769.2023.10321875

3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect. / Serunjogi, Solomon; Sanduleanu, Mihai.
2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. IEEE Computer Society, 2023. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Y1 - 2023

N2 - This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125GS/s with 4.9 ENOB and a Walden figure of merit of 109fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2mW from a 1V supply. It was realized in the 45nm PDSOI from Global Foundries.

AB - This paper presents a flash, Time Domain ADC with T/H amplifier, Voltage Controlled Delay Line and Time to Digital Converter. The design is operating at 3.125GS/s with 4.9 ENOB and a Walden figure of merit of 109fJ/Conversion. Automatic calibration means are provided as well. For measurements purposes, an integrated memory is provided. It consumes 16.2mW from a 1V supply. It was realized in the 45nm PDSOI from Global Foundries.

KW - Backplane interconnect

KW - Gigabit Radio

KW - mm-Waves

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KW - Track and Hold

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M3 - Conference contribution

AN - SCOPUS:85179855827

T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

BT - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023

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Y2 - 16 October 2023 through 18 October 2023

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3.125GS/s, 4.9 ENOB, 109 fJ/Conversion Time-Domain ADC for Backplane Interconnect

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