Digital ASIC Design



ASIC design flow: role of HDL in ASIC design. HDL coding style for synthesis. ASIC testing and testbench creation. Clocking in ASIC design. ASIC libraries. Constraints for synthesis. Static timing analysis (STA), statistical timing analysis and chip variation. Floor-planning. Place and Route of ASICs. Parasitics, noise, and cross talk. Chip filling and metal filing. Timing closure and tapeout. Fault models, test pattern generation and design for testability techniques. The course will use state of the art EDA (Electronic Design Automation) tools such as Cadence and Synopsys.

Course period3/02/14 → …